OTFC-LSTM: An Efficient Design of LSTM Accelerator based on On-The-Fly CORDIC

Long short-term memory (LSTM) networks are frequently applied to the long time sequence tasks, such as natural language processing (NLP), automatic speech recognition (ASR) and long-term time series forecasting (LTSF), due to its superior memory properties. Nonlinear activation functions that simulate the behavior of neurons are ubiquitous in LSTM, and previous experiments have shown that high-precision nonlinear functions can contribute higher accuracy significantly. However, current hardware implementations of LSTM have been suffering the issues like low accuracy and large resource consumption. In this paper, we propose a hardware implementation of the on-the-fly coordinate rotation digital computer algorithm (On-the-fly CORDIC, OTFC) to compute the Sigmoid and tanh activation functions, which decreases the computation cycle by more than 50% and greatly reduces the resource consumption while ensuring a minimum accuracy loss. Based on this algorithm, a hardware architecture that can be configured to LSTM layer is developed, making it suitable for low power time series computing scenarios. The proposed hardware architecture validated on Xilinx ZYNQ-7020 FPGA achieves a low resource utilization with 2.46 GOPS throughput rate in 12-bit and 0.274 W power for MNIST dataset.