GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process

DDR5 SDRAMs have many requirements of duty cycle, system voltage, slew rate, etc., so that a specialized design approach for FinFET-based I/O buffers is needed. Genetic algorithm (GA) was used to model process, voltage, and temperature (PVT) variations to determine how temperature and voltage affect the I/O buffer’s characteristics. Interestingly, the study found that the temperature detector circuit was unnecessary, saving power and space. However, voltage variations significantly affected the slew rate. A new Voltage Detector circuit using ultra-low threshold voltage (ULVT) transistors was introduced. The innovative Voltage Level Converter circuit, Pre-Driver, and Digital Logic Control circuits improved the slew rate and throughput while stabilizing Output Buffer Stage. TSMC’s 16-nm FinFET CMOS technology implemented the I/O buffer, where its core area was 0.19339×0.056957 mm
²
. The device operated reliably at 6.0 Gbps, with a slew rate of 8.93 V/ns (0.8 V VDDIO) and 14.7 V/ns (1.2 V VDDIO maximum), and a duty cycle of 48.4% (0.8 V VDDIO) to 51.8% (1.2 V VDDIO maximum). By auto-tuning the driving current, high and low voltage modes attained a 19% and 30% increase in SR improvement, respectively.