High-Performance Reed-Solomon Decoder for Chiplet Interconnection

This paper proposes a Reed-Solomon (RS) code decoding algorithm for the Chiplet interconnection based on the forward error correction (FEC) coding technique, giving a high fault-tolerance die-to-die (D2D) adapter layer in the Chiplet interconnection protocol specification. The algorithm utilizes CRC check, error correction, retransmission, and other functions to ensure high reliability in data transmission. Also, a Reed-Solomon code decoder architecture for Chiplet interconnection is designed to meet the interconnection interface transmission rate index. This architecture produces rapid error correction and data retransmission of codewords with codeword decision and retransmission decision mechanism. The proposed decoder is implemented and synthesized with Semiconductor Manufacturing International Corporation 0.13-um CMOS technology library by Design Compiler. The synthesized results show that the proposed decoder requires an area of 45.1k XOR gates, and the throughput rate can reach 108Gbps.