On the Understanding and Modeling of Non-Negligible Subthreshold-State Degradation (SSD) in Sub-20-nm DRAM Technology

Based on the sub-20-nm DRAM technology, the peripheral transistors under stress in the subthreshold-state degradation (SSD) are investigated for the first time. A completely new phenomenon, two-stage degradation, is observed, which can not only exhibit large degradation even comparable to channel hot carrier (CHC) stress mode but also introduce severe device-to-device variation. The novel mechanism of positive-feedback-induced second-impact-ionization is revealed as the root causing such an issue. Based on the understanding, a defect-based two-stage new model is proposed and validated. Since SSD can occur during every AC switching, they must be taken into consideration in future device- and circuit-level reliability assessments.