A Scratchpad Spiking Neural Network Accelerator

Spiking Neural Networks (SNNs) have recently been used as a computational model for applications such as deep learning, image recognition and machine learning. Similar to the biological brain, SNN neurons depend on the membrane level to fire an output. If the level exceeds a specified threshold, the neuron sends an output to activate next neurons. This leads to an unbalanced workload among the neurons. The dynamically-changing membrane level is stored inside a neuron. In hardware, this storage can be implemented as a register or on-chip memory, which determines the amount of consumed resources and, in turns, affects the network scalability. SNN accelerators have recently been implemented on UltraScale FPGAs devices for high-performance purposes. On-chip memories on these devices are classified as distributed memory, Block RAMs (BRAMs) and Ultra RAMs (URAMs). In this paper, we explored the impact of using different on-chip memories to store the membrane level of SNN neurons. We implemented a parameterizable SpIking Neural networK (SINK) accelerator where the network capacity and weight_width are parameters. SINK has the ability to run in four different modes based on the memory type. We ran SINK on UltraScale Zyncl04 FPGA device and measure the utilization of the hardware resources (LUTs), registers, memory, power consumption and performance. The results show that URAM can be the best fit to store the membrane level, since it used 30%, 11 % and 2% less LUTs, Regs, and power 2% respectively comparing with BRAM and distributed memory