Optimization and Implementation of SR T -16 Floating-Point Divider Based on FPGA

Currently., there is a significant absence of FPGA or CPLD chips with integrated floating point division IP cores or high operational accuracy., such as China's Gowin and Ziguang Tongchuang FPGA chips. These chips are widely utilized due to their affordability; however., the lack of division components or IP cores restricts the popularization and application of multiple information processing systems. This paper will presents an optimization of the traditional SRT-16 divider by proposing a parallel structure that shares partial remainder and quotient number selection functions to reduce circuit area., and the optimized algorithm is successfully implemented on the PGL22H chip from Ziguang Tongchuang company. Through the modelsim simulation and system test verification., it accurately outputs floating point quotient values with a delay of 8 cycles for single precision and 16 cycles for double precision calculations. In terms of resource utilization., compared to the traditional SRT-16 approach., this optimized design reduces the number of L UTs by 24.71 % and flip-flops by 36.16%. This method can be effectively applied to system development and provides a solution to the problem of lacking floating-point division component.