Low Power S-Box Architecture for SM4 Algorithm

In implementating the SM4 algorithm on ASIC, the Substitution Box (S-Box) emerges as a critical component facing significant power consumption challenges. This is primarily due to the S-Box's requirement to compute multiplicative inverses in the Galois field and perform affine transformations with matrices to minimize the correlation between input and output data, a process essential for ensuring data security but simultaneously increasing power consumption. Traditional implementations of the S-Box rely heavily on dense combinational logic operations, leading to low circuit efficiency and excessive power consumption. Regarding this issue, our research adopts an optimized one-hot encoding strategy. Compared to traditional one-hot encoded S-Box implementations, our approach successfully reduces power consumption and area overhead by 6% and 18.67%, respectively. Building upon this strategy, we propose a novel low-power S-Box architecture. This architecture, in comparison to the conventional binary-coded lookup table method, reduces power consumption by 5.45%. This significant reduction enhances the overall power efficiency of the SM4 algorithm circuit, demonstrating a substantial improvement in addressing the high-power consumption challenge inherent in S-Box operations.