Design of a Vedic Multiplier based 64-bit Multiplier Accumulator Unit

VLSI (Very Large-Scale Integration) Design is a process of designing integrated circuits (ICs) by integrating millions or even billions of transistors on a single Silicon wafer. The three main corner stones of VLSI system are area, power and delay. Low-Power VLSI is a niche field in which recent advancements are happening. One of the main applications of low-power VLSI is a Multiply Accumulate (MAC) unit which is extensively used in signal processing. This brief presents a Verilog implementation of a 64-bit MAC unit implemented using a Vedic sutra Urdhva Tiryagbhyam. The proposed methodology has produced 39.7% delay efficient, 32.5% area efficient and 27.6% power efficient results compared to a conventional MAC unit.