A Novel Degradation Mechanism of SiC Power Devices Under Electro-Chemical Stress

The goal of this work is to assess the failure mechanisms of SiC MOSFETs after long term H3TRB testing. For that purpose, an H3TRB test was performed on power modules with SiC MOSFET chips until all devices reached their parametric end-of-life. The results of the failure analysis showed that all tested chips exhibit vertical cracks through the chip near the edges. A chemical analysis suggests that the cracks originate from oxidation near the edges of the chip. The resulting volume increase, caused by the oxidation process, lead to mechanical stress and eventually the formation of vertical cracks of the SiC crystal in the respective area. Since this effect is not known for silicon devices, this could be a novel degradation mechanism, possibly unique to SiC. Even though the characteristic lifetime of the failure distribution is much longer that typical qualification criteria the acceleration factor with respect to field conditions is yet unknown and thus, should be further investigated.