Impact of Circuit Mismatches and Parasitic Parameters on Paralleling 650-V E-Mode GaN HEMTs

In the high-power applications, paralleling multiple and small die size devices is commonly accepted instead of single large die size device due to the yield and reliability limitation. This paralleling methodology has been mature for the Si and SiC devices. However, the fast switching speed of GaN high electron mobility transistors (GaN HEMTs) makes it very sensitive to parasitic parameters and thus paralleling GaN becomes a challenging topic. In this paper, the impact of circuit mismatches and parasitic parameters on paralleling 650-V GaN enhancement-mode (E-mode) HEMTs with an analytical model is proposed. Furthermore, the design consideration and the most important parasitic parameters with asymmetric layout are presented to achieve a reliable switching process. The importance of parasitic parameters is different with or without the current shunt resistance. The proposed layout is modeled in Ansys Q3D to extract the parasitic parameters. The Ltspice simulation and double pulse test (DPT) experiments at 400V/20A are done to verify the proposed layout of paralleling GaN HEMTs.6