Vertical Stacking of Heterogeneous Chiplets of Duplexer on LNA/SOI

A demonstration of vertically stacked heterogeneous chiplets featuring Duplexer and LNA/SOI is showcased in this work demonstrating the possibilities in miniaturizing RF front-end modules. By placing the duplexer on LNA/SOI, a simple 3D stacked package with Through-Silicon Via (TSV) in the LNA/SOI enables vertical connectivity between the chiplets. This paper provides an in-depth exploration of the design considerations for chiplet stacking, RDL layout, and TSV placement on LNA/SOI to ensure optimized RF performance of the stacked duplexer and LNA/SOI. Additionally, it covers key aspects of wafer fabrication processes, C2W bonding assembly, and mechanical analysis on wafer warpage. The paper also presents the results of frequency domain functional testing for the stacked duplexer on LNA/SOI, as well as package reliability testing outcomes under MSL3, TC500, and TCoB 500.