Implementation of Dynamic Comparator Using Improved Diode Free Adiabatic Logic Design

The development of VLSI technology has led to an increase in the demand for portable devices that enable multimedia and offer high-speed computing. Low power design solutions are now needed because of significant power dissipation. Dynamic comparators are essential components of high-speed ADCs because they process and compare analog signals rapidly and accurately. These comparators have features like regenerative feedback, fast speed, low power consumption, and high input impedance. Adiabatic logic approaches are used to reduce power consumption, and a comparator based on Diode Free Adiabatic Logic (DFAL) is developed, which reduces power. To build dynamic comparators, and to reduce power significantly this study presents IDFAL (Improved Diode Free Adiabatic Logic) comparators and compares its performance metrics with those of DFAL. Using Spectre simulator to simulate the design, Cadence Virtuoso is used for circuit design in gpdk 90nm technology.