Design and Evaluation of 32-Bit N-Tap FIR Filter for Audio Processing Applications

The following document presents an exploration of the design and implementation of floating-point Finite Impulse Response (FIR) filters. The design process involves the selection of appropriate filter specifications, including filter order, passband and stopband frequency ranges, and desired frequency response characteristics, employing the Hamming windowing technique. FIR filters play a crucial role in digital signal processing across various applications such as audio and image processing, communication systems, and biomedical signal analysis. Notably, FIR filters are known for their stability and linear phase response, making them well-suited for real-time signal processing tasks. The designed FIR filters encompass various tap numbers, including 4, 8, 16, 32, and 64 taps, with input, output, and filter coefficients represented in single-precision IEEE754 format. These designs are modeled using Verilog Hardware Description Language (HDL) and implemented on a Kintex-7 FPGA with part number XC7K70TFBV676-1, utilizing the Xilinx Vivado Tool. The evaluation of these designs includes parameters such as incurred delay and power dissipation. The results indicate that the proposed architecture outperforms integer-based FIR filters as the number of taps doubles for accurate filtering. Specifically, the area reduces from 58.72% to 49.77%, and the delay decreases from 58.04% to 46.95%. However, there is a trade-off as power dissipation increases by 45.41 % to 47.85%.