A Research on Power Meter Board-Level Systems with Strong EMC Anti-Interference Capability

This study investigates the reliability issues of power metering chips in the presence of strong electromagnetic interference (EMI) environments. By utilizing an electrostatic field meter to simulate external interference, we examined the coupling strength of the interference signals on the critical paths. It was found that the paths exhibited insufficient immunity to electromagnetic waves, resulting in the introduction of noise in the range of 0-500MHz exceeding 1Vpp. Based on these findings, we propose the addition of appropriate electromagnetic attenuators to the critical paths. Simulation results indicate that the reception of a significant amount of interference signals is due to factors such as PCB designs with excessively long traces and the absence of RF circuits. Experimental results demonstrate that, following the improvements, the interference level decreased from the original 2ppV to 0.1Vpp, and the operating frequency was increased from 100MHz to over 500MHz. The study will present comprehensive analysis results and testing data.