Sub-10nm Standard Cell Library Design Methodology for On-Grid Pin Accesses

On-grid pin access is necessary for 1-D regular layout design. It is also instrumental to detailed routing efficiency. As semiconductor technology advances, on-grid pin access becomes a distant goal due to increasing discrepancy between contacted polysilicon pitch (CPP) and M1 pitch (M1P). Though the multiple-layout approach to this problem was proposed for some specific case, no investigation into its impact on chip-level routing is found. In this paper, we generalize the multiple-layout approach. We design a 7.5-track standard cell library for the case of the ratio CPP/MIP = 3/2 to study the impact of the multiple-layout approach on chip-level routing. The experiments for this specific case show that the multiple-layout approach can achieve not only on-grid pin accesses but also 46% to 83% fewer DRC violations with 28% to 50% less runtime at the expense of 5% to 13% increase in the longest path delay. If on-grid pin access is a must, the increase in the longest path delay is the price for fulfilling such a requirement.