A 105-dB SFDR 16-bit SAR ADC with a Window Capacitor Calibration Scheme

A 16-bit 1-MS/s SAR ADC was fabricated in 180nm digital CMOS. To maintain excellent linearity, a window capacitor calibration (WCC) scheme is proposed to estimate capacitor mismatch and obtain corrected bit weights. Different from prior calibration schemes, the WCC scheme can alleviate the offset and flicker noise effects on the calibration accuracy. The total input capacitance is only 4.8 pF. This ADC consumes a total power of 0.91 mW from a 1.8-V supply and occupies an active area of 0.276 mm
²
. After using the proposed WCC scheme, measured INL is improved from -103/+106 LSB to - 1.3/+1.7 LSB. Measured SFDR and SNDR are 105 dB and 83.8 dB, respectively. This prototype ADC achieves a Schreier FOM of 172 dB.