A GaN Driver with Almost Constant dv/dt during Miller Plateau for V-I Overlap Loss Reduction

When driving a GaN switch, the maximum transition speed of drain-source voltage (peak dv/dt) should meet specification. But reducing the peak dv/dt usually exacerbates V-I overlap loss. This work presents a GaN driver for buck converter featuring: 1) voltage-controlled peak dv/dt; 2) almost constant dv/dt during Miller Plateau (MP) for reducing V-I overlap loss. We analyze why a constant dv/dt minimizes V-I overlap loss under a peak dv/dt specification, how to maintain a constant dv/dt during the MP period, and propose an implementable solution. We use a sensing block to judge whether the peak dv/dt violates the specification, and an adaptive searching scheme to find out the key parameters for the targeted constant dv/dt. We designed the layout with a 180-nm SOI process, and simulation results show that the peak dv/dt is well under control. It saves up to 33.99% V-I overlap loss when compared with the conventional constant current driver scheme.