Nonlinear Analysis of Quadrature Switched-Capacitor Power Amplifier and Digital Predistortion

This paper presents a modified vector combination (MVC) model to analyze the nonlinearity behavior in the quadrature switched-capacitor power amplifier (SCPA), which improves model accuracy while reducing the number of recorded points and iterations compared to the two-dimensional (2-D) LUT-based model. To analyze the nonlinearity caused by efficiency enhancement techniques, high-order Taylor series are applied to meet the model accuracy requirement. Moreover, a two-stage process with MVC and general memory polynomial (GMP) digital predistortion (DPD) is introduced to calibrate the static nonlinearity and memory effect, respectively. In the measurement, a 15-bit transformer-based quadrature SCPA chip with Class-G and IQ-cell-sharing techniques is implemented in 28nm CMOS and employed to verify the effectiveness of the MVC and two-stage DPD methods. For the 802.11ax 40MHz 64QAM signal at 2.4GHz, this chip achieves up to −40.9dB error vector magnitude (EVM) floor and significant EVM improvement even at deep power back-offs after the DPD.