FPGA Implementation of CNN Accelerator with Pruning for ADAS Applications

Convolutional neural network plays a prominent role in computer vision applications such as advanced driver assistance systems which demand high accuracy and low latency. The need for low latency, resource limitation and power constraints are the major complexities that are associated with the deployment of the computationally intensive convolutional neural networks in ADAS applications. In this paper, an efficient CNN accelerator is implemented on Xilinx PYNQ-Z2 FPGA Board for traffic sign recognition. The CNN model is further accelerated by pruning the weights of the filters which has very little effect on accuracy. The experimental results show that the proposed method effectively achieves 5.65 times speed in terms of execution time with only 0.33 times drop in accuracy on LeNet-5 architecture.