Testing and Fault Diagnosis for Multi-level Resistive Random-Access Memory in Monolithic 3D Integration*

The integration of resistive random-access memory (RRAM) with emerging monolithic 3D (M3D) integration technology offers the promise of lower cost per bit and higher memory density than current technologies. Multiple bits per RRAM cell, i.e., multi-level cell (MLC), further enhances memory density and reduces power consumption. However, MLCs are susceptible to errors due to power supply noise (PSN) within the power delivery network. In addition, monolithic inter-tier vias (MIVs) in M3D-integrated MLC designs are prone to manufacturing defects as they penetrate through a device tier between memory cells and access memories. These defects impact the voltage level at the inputs of an MLC, resulting in incorrect read/write operations. Therefore, testing and fault diagnosis for M3D-integrated MLC RRAM is important to detect defective cells and facilitate yield learning. We present a detailed analysis of RRAM faulty behaviors in the presence of PSN and MIV defects. We also introduce a March sequence to detect faults due to PSN noise and quantify the magnitude of noise and defects. Experimental results for MLC RRAM cells demonstrate the effectiveness of the proposed test and diagnosis solution.