Flash memory revolution: journey from 2D to 3D, migrating to modular memory fabrication

The technological history is discussed from the birth to the present of 3D flash memory. Further high memory density of 3D flash memory is driven by increasing the number of word line (WL) stacking. The challenges for higher stacking are: significant difficulty of high aspect ratio structure processing including stress control, lower cell current, increased area of connection between WL drive circuit and WL, so called staircase, and so on. Economic issues what we have to discover technical and/or operational solution in near future are higher process cost due to an increase in the number of layers and a lengthening of turnaround time (TAT) by increasing in process steps. As one of optimal solution for a 2xx generation, three key technologies are introduced, which don't rely on higher stacking as follows: CMOS directly bonded to array (CBA), super-multiple staggered memory hole layout and on-pitch select gate drain-side (OPS).