Self-Heating and Process-Induced Threshold Voltage Aware Reliability and Aging Analysis of Forksheet FET

Sheet/channel wrapping by the low-thermal conductive material, sheet stacking, dielectric wall (DW) for N/P separation, etc., puts a few vital reliability concerns in stacked Forksheet (FS) FET. Thus, using a well-calibrated TCAD setup, this paper presents a detailed investigation of the self-heating effect (SHE) and process-induced ‘change in threshold voltage (V
th
)’ based lifetime prediction of FSFET. Through extensive simulations, we analyzed: (i) the role of SHE within N/P and beyond DW; (ii) the impact of random dopant fluctuation (RDF) on ION & V
th
for distributed samples; (iii) the impact of metal grain granularities (MGG) and ratio of grain size to gate area (RGG) on V
th
variation; and finally, (iv) the benchmarking of devices' aging, i.e., lifetime prediction (LTP), defined by
$\mathrm{V}_{\text{th}}= \pm 50\text{mV}$
. Thus, the proposed design space exploration unveils the guidelines for reliable FSFET operation and predicts early aging.