A Low-Jitter Phase Detection Technique With Asymmetric Weights in Multi-Level Baud-Rate CDR

A change from a non-return-to-zero (NRZ) signaling to a four-level pulse amplitude modulation (PAM-4) signaling causes various challenges in clock and data recovery (CDR) designs as well as analog-front-end (AFE) designs. A PAM-4 CDR with a 2x-oversampling phase detector (PD) has an issue of increased pattern-dependent jitter due to asymmetric transitions. This work investigates a similar problem in a baud-rate CDR by analyzing the PD characteristics. In the PAM-4 baud-rate sampling, the transitions are classified into two types: full-swing transitions and non-full-swing transitions. Since utilizing the non-full-swing transitions can affect the jitter tracking ability, careful consideration of decisions using these transitions is necessary to optimize the jitter performance. To address this issue, we propose an asymmetric-weighted PD that minimizes pattern-dependent jitter and maximizes a transition density by utilizing both the full-swing transitions and the non-full-swing transitions. Using a pseudo-linear analysis, the proposed PD achieves improved jitter performance compared to the conventional PD. Fabricated in 28-nm CMOS process, a prototype PAM-4 receiver with the proposed CDR is demonstrated at 40 Gb/s. The CDR achieves a bit error rate (BER) less than 10
$^{-9}$
and an energy efficiency of 1.65 pJ/b.