A Comparative Analysis of Robust Level Shifters for High-Speed and Ultra-Low Power Applications

A comparison of different voltage level shifters is presented in this work. Depending on the requirement, a voltage level shifter can transform the voltage between different voltage domains. The level shifters are implemented with different techniques like the use of the capacitor and diode-connected tran-sistors for reducing the contention between the complementary devices of the output buffer. The reduced contention majorly helps in achieving reduced short-circuit power dissipation. These techniques ultimately help in increasing the speed, reducing the power dissipation and widening the range of input voltage level. The major focus of the comparison is on the delay and power consumption. Simulations have been carried out using Cadence Virtuoso tool. The analysis shows that how the different techniques applied in the works have helped us to reduce the power as large as 2.31 uW to much smaller value of 170.63 pW. This drop in power is obtained at the cost of delay, with delay numbers changing from 24.48 ns to 74.66 ns. The paper aims to demonstrate how the trade off exists between the delay and power and how different techniques are applied in controlling these parameters. The comparison is done focusing the techniques of implementation while measuring their power and delay values.