Self-Timed Counter Implementation Basis

The article researches the problem of self-timed (ST) binary counter implementation. ST circuits demonstrate correct operation over a much wider range of supply voltage and ambient temperature, in contrast to synchronous counterparts. The reason for this is hardware redundancy, two-phase operating discipline and mandatory acknowledging of the switch completion of all circuit cells in each phase of circuit operation. As a result, ST circuits operate stably no matter the cell delays. Due to their simpler indication, serial ST counters have less hardware redundancy than combinational ST circuits. However, they require the specific procedure organization to implement ST preset. The article examines the circuitry basis for the ST counter implementation and proposes a schematic preset realization ensuring its self-timing and optimal hardware complexity.