Fault-Current Limiting Strategy for Grid-Forming Converters With Virtual Impedance From Both Inner CCL and Outer VCL

With the improvement of the control strategies of grid-forming converters (GFMCs), the quantity and dimensions of semiconductor components continue to increase, resulting in GFMCs unable to withstand large currents during grid faults like traditional synchronous generators (SGs). Therefore, the fault current limitation of GFMCs during grid faults has become a research priority. This paper proposes a current limiting strategy for GFMC based on dual-loop-feed virtual impedance (VI). The strategy introduces voltage compensation into both the outer voltage control loop (VCL) and inner current control loop (CCL), resulting in an enhancement of the inverter's output impedance and the response speed of current limiting control. In contrast to conventional current-saturation methods, the proposed strategy maintains the characteristics of a voltage source converter (VSC) while limiting the fault current. Finally, the proposed strategy is verified in a simulation model. The simulation results conclusively illustrate that the proposed VI-based current limiting strategy efficiently mitigates ac current during three-phase short-circuit faults and improves the stability of GFMC during fault transients.