A 86 mW of Power, 1.57 dB of Noise Figure, Low-IF CMOS Receiver Front End for Sub-6 GHz Applications

In this work, the functionality and performance of low-IF receiver is studied using a RF frequency band of 3.4-3.45 GHz and LO frequency of 3.4 GHz. The low noise amplifier, mixer, low pass filter, buffer, sample and hold, analog to digital converter is integrated. The simulations were performed using 40 nm RF CMOS technology. The performance in terms of noise figure, power gain and power consumption are compiled to compare the performance of the receivers that are available in literature. The low IF receiver frontend has been used and investigated for sub 6 GHz applications. In the first stage three stage LNA where the output is taken differentially and the second stage is mixer in IF architecture and mixer is connected to filter. The last stage is a four bit flash ADC, and the output is taken differentially. The power and noise figure of the receiver is approximately 86mW and 1.57dB respectively.