Routing Congestion Prediction in VLSI Design Using Graph Neural Networks

This paper considers the problem of estimating the congestion map in the early stages of VLSI layout design of digital blocks by applying graph neural network model. Early prediction of congestion violations will allow the layout engineer to modify design block characteristics such as floorplan, macro placement and input-output ports placement to prevent interconnect routing issues at later stages, thereby reducing the number of CAD runs and overall circuit design runtime. The application of graph neural networks allows to take into account additional information about the connections of elements in the netlist for more accurate prediction.