Modelling the Effect of Output-Dependent Integrator Gain on the Unadjusted Error of Inverter Based 1stOrder $\Sigma\Delta$ ADC

Substantial instances of compact low-cost 1
^st
order
$\Sigma\Delta$
ADCs are used to measure, monitor, and debug various near DC analog voltages present in large SoCs. The modulator outputs are accumulated and dumped as converted digital values using these ADCs. As calibration at high volume use-case is inefficient, unadjusted outputs are often used as final measured values. The integrator of this ADC uses limited gain inverter as its amplifier for cost efficiency. The inverter gain also varies with respect to the integrator output, giving rise to larger nonlinearity. The effects of non-linear gain of the inverter on
$\Sigma\Delta$
ADC are analyzed in this paper. The output dependent gain is modelled in the MATLA
$\mathbf{B}$
™ using lookup table approach. The additional quantization error due to gain variation is elucidated to estimate maximum achievable accuracy with respect to oversampling ratio of the ADC. The analysis is validated by measurement data from the IP designed in sub-10nm technology.