A 17 GHz Output PLL-Based Frequency Doubler with -60dBc Fundamental Spur

Frequency doublers are used to obtain a higher carrier frequency from a high-quality lower frequency source. The low-frequency phase noise of the original source is preserved because of the high bandwidth of the doubling process. This can be easier than designing a high-frequency oscillator and phase-locked loop with correspondingly low phase noise. Frequency doubling can be accomplished using an even-order nonlinearity, injection-locked oscillator, or a phase-locked loop (PLL) doubler. Due to an additional order of filtering offered by the loop filter, a PLL frequency doubler results in a lower leakage of the fundamental input to the output. This work presents a PLL-based doubler provides with a 17 G Hz output and a -60 dBc leakage at 8.5 GHz. The loop bandwidth is 50 MHz. At 1 MHz (10 MHz) offset, the open-loop VCO and the closed-loop PLL have an output phase noise of -107.7 (-131) dBclHz and -117.6 (-134.7) dBclHz, respectively. The excess phase noise beyond the multiplication factor is 0.1 dB (1.3 dB) at 1 MHz (10 MHz) offset. With an input jitter of 196 fs (1 kHz to 100 MHz), the output jitter is 202 fs implying a 50 fs excess jitter due to the PLL multiplier. The prototype chip in 130 nm SiGe BiCMOS process occupies 1 mm
²
and consumes 180 m W from a 3.3 V supply.