FPGA based I-FIR Non-uniform Filter Banks

A low-complexity non-uniform filter bank based on Interpolated-Finite Impulse Response(I-FIR) filter for the receiver in the DVB-RCS2 reverse link is introduced. We firstly demonstrate the efficient I-FIR technique to design the high stopband attenuation prototype filter with a lower order than conventional methods of Equiripple and Least-Squares. Subsequently, we present the structure of I-FIR non-uniform filter bank, illustrating the application of the I-FIR technique in filter bank design. Furthermore, this paper outlines the hardware architecture for the unique I-FIR filter bank. We employ a commutator instead of conventional delay lines and downsampling structures in each path of the filter banks. In the hardware architecture, the commutator can be realized using the IP core known as FIR Compiler, providing significant convenience for obtaining the filter banks. We conduct simulations to evaluate the proposed non-uniform filter bank’s performances and showcase its frequency response. The superiority of the I-FIR technique and benefits of implementing this filter bank for the receiver in the DVB-RCS2 reverse link are demonstrated. In addition, we present an example detailing the computational load and resource utilization of DSP48s and RAMs within the I-FIR filter bank.