Ultra-Low Power 60 GHz Class-C Frequency Tripler in 22-nm FDSOI CMOS Technology

This paper presents a 60 GHz class-C frequency tripler, implemented in 22-nm FDSOI (fully depleted silicon-on-insulator) CMOS technology, for ultra-low power and highly integrated radios used in millimeter-wave indoor localization applications. The tripler employs a multi-stage transformer-coupled differential design with band-pass filters to selectively extract and amplify the power at the 3rd harmonic
$(3\mathrm{f}_{0})$
tone while attenuating powers at fundamental
$(\mathrm{f}_{0})$
and second harmonic
$(2\mathrm{f}_{0})$
tones. An integrated bias generator with resistor trimming, improves the tripler robustness to the on-chip process and mismatch variations. The tripler exhibits a maximum conversion gain (CG) and peak conversion efficiency (CE) of -0.7 dB and 12.63%, respectively, at 60 GHz, and a 3-dB bandwidth of 3.6 GHz with a total DC power consumption
$(\mathrm{P}_{\text{DC}})$
of 7.9mW at 0.8 V supply. A harmonic rejection ratio (HRR) exceeding 45 dB for fundamental and second harmonic tones is achieved. The maximum saturated output power
$(\mathrm{P}_{\text{SAT}})$
obtained is 0.9 dBm. The circuit occupies 0.
$4 \text{mm}^{2}$
area, including pads.