FPGA Implementation of Correlator for Direct Sequence Spread Spectrum (DSSS) Systems

Spread Spectrum (SS) technology utilizes pseudo-noise codes to spread signal energy over a wider bandwidth, independent of message signal bandwidth. Direct Sequence Spread Spectrum (DSSS) employs pseudo-noise sequences synchronized at the receiver to "despread" the signal, with chip rate and baseband filtering affecting transmitted bandwidth. This paper presents the implementation of a spread spectrum correlator for DSSS systems using VHDL and FPGA synthesis. The correlator comprises digital matched filters, coefficient control logic, and output processing units. An external host processor configures the matched filter coefficients, while a DSSS spreader generates test signals. The FPGA architecture is explored for high-performance synthesis of matched filter blocks. Simulation in ModelSim and synthesis using Xilinx Synthesis Tool (XST) for Spartan3E family FPGA (XC3S500E) are conducted. Xilinx Placement & Routing tools handle design optimization and I/O routing. Post-backend netlist simulation ensures timing verification. The study investigates the advantages of digital correlator over analog counterparts, providing insights into optimizing spread spectrum systems for FPGA implementation.