A novel approach to 3D stacking of power chips with hot-via interconnections

Eutectic bonding is the primary method of integrated packaging for achieving efficient heat dissipation in power chips. However, for specialized power chips for wire-free packages with hot-via interconnections between upper layer and the backside pads on the lower layer, achieving high-precision, zero-damage, and highly reliable eutectic bonding is challenging using conventional equipment and methods. This paper proposes a simple and efficient approach that employs a specially designed Si-based fixture and thermocompression bonding process to achieve eutectic bonding of such kind of power chips. The fixture is fabricated using MEMS technology and comprises two layers: a structural layer and a thermal barrier layer. The structural layer features numerous micro-cavities that enable effective avoidance of air bridges when power chips are placed face-down. The thermal barrier layer assists in controlling the temperature of the solder layer during back-end co-soldering, thereby enhancing the reliability of the solder joint. Finite element simulations were carried out to analyze the heat transfer path during the eutectic process. The results indicate that when the thickness of the barrier layer is 200 micrometers, the temperature of the bonding tool reaches 300℃, while the temperature of the solder layer reaches 280℃. Finally, we fabricated samples and conducted X-ray inspection, which showed satisfactory results in terms of alignment accuracy and soldering quality. This provides a feasible solution for high-precision and high-quality automated eutectic bonding of power chips in wire-free 3D stacking packages.