Thermal multiscale simulation of a FO-WLP SiP including a GaN Power Amplifier

This paper describes some of the multi-physics, multi-scale simulation activities carried out as part of the SMART3 project. The main objective of this project is to evaluate and develop a new generation of 2D and 3D packaging to address the heterogeneous integration of different semiconductor technologies to design fully integrated systems [SiP]. Fan Out Wafer Level Packaging (FO-WLP) [1] is the packaging technology considered in this project. We propose to illustrate this work through the study of a test vehicle including a GaN Power Amplifier (PA) with two temperature sensors packaged with this technology. First, we will introduce the 3D object construction method. Then, we will examine the thermal simulation results for this test vehicle, with the aim of establishing the test and reliability conditions in practice. A first thermal study will be presented for a GH15 transistor [2] isolated from the overall structure to validate the device level design used for the PA. In a 2
^nd
step, we will move to the results obtained for the SiP and finally, we will present the results of the SiP assembled on a PCB.