Concise Yet Efficient Hardware Design of a Quantum Coprocessor

This work proposes a customizable hardware design of a coprocessor that is able to perform quantum computations, exploring pure parallelism as well as a pipelined execution. The architecture is based on a quantum state memory, a scratch memory, a calculation unit, a measurement unit and, a control unit. All functional units communicate with each other via dedicated and shared data buses, depending information exchange frequency. The design is simulated and proven to be effective in executing quantum operations.