Phase frequency detector with zero-reset pulse for low-spur Phase-locked loop applications

This paper focuses on the reduction of spurious tones (also referred to as “reference spurs”) in the clock generated by a phase-locked loop (PLL). The spurious tones in the clock lead to a phenomenon known as “reciprocal mixing;’ which places stringent spurious tone requirements in Radio frequency (RF) applications. The majority of the spurious tones are caused by the current mismatch and timing mismatch between the UP and DOWN current sources of the charge pump (CP), which are turned ON simultaneously due to the presence of a reset pulse in the phase frequency detector (PFD). This paper proposes a novel zero-reset pulse PFD that avoids the simultaneous turning ON of the CP switches. For the purpose of comparison, the proposed novel PFD and the existing PFD topologies namely conventional PFD, differential PFD, true single-phase clock-based PFD, and pass transistor-based PFD with delay cells, are implemented and simulated in the Cadence spectre environment using the UMC 180 nm CMOS with a supply voltage of 1.8 V. From the simulation results, it is observed that the proposed PFD-based PLL achieves a lower reference spur of -80dBc/Hz at 100 MHz offset for a 1.6 GHz PLL. The zero-reset pulse PFD consumes a power of 22 $\mu$W when operated at a frequency of 100 MHz. It occupies an area of 285 $\mu m^{2}$.