MIST: Many-ISA Scheduling Technique for Heterogeneous-ISA Architectures

Heterogeneous chip multiprocessors have shown significant promise in achieving better performance and energy efficiency than their homogeneous counterparts. Instruction set architecture (ISA) as a heterogeneity dimension has become increasingly popular in recent years due to the significant performance gains it offers. In order to achieve maximum benefits from heterogeneous-ISA architectures, a program must be divided into phases, with each phase then dynamically scheduled on the most affine ISA core. Determining the affine ISA for every program phase from numerous ISAs at runtime is crucial, as a larger set of ISAs enhances the potential of heterogeneous-ISA architectures. This work proposes MIST, a classification-based scheduling algorithm with minimal hardware overhead for many (more than two) ISA scenarios. It utilizes a smaller set of microarchitectural parameters obtained via online performance counters to determine the most affine ISA for upcoming program phases. Overall, MIST achieves a prediction accuracy of 88.1%, resulting in a 40.4% improvement in single-threaded performance compared to x86 ISA architecture. It achieves 9.9% additional performance gain compared to the current state-of the-art scheduling technique.