A Technique to Optimize Clock Latency after CCOpt exploiting Useful Skew

A crucial phase in the physical design flow is clock tree synthesis (CTS). CTS constructs the clock tree by balancing the skew throughout the design for every clock present. Because of the shifting technology nodes and the resulting increased complexity of integrated circuits, the traditional flow of CTS during CCOpt is inefficient in many places. The analysis of effective CTS methods for the best timing convergence in SoC implementation is the main goal of this work. Exploiting useful skew and manual modification of buffer chain in clock path are the approaches used for clock delay reduction to enhance device performance.