Design and Analysis of 3-Phase Hybrid Asymmetric Multilevel Inverter Topology with Reduced CMV

In recent years Multilevel Inverters (MLI) have emerged as the most efficient and most promising inverters in industries and commercial applications. The variable speed drives (VSDs) connected to MLIs have replaced the need for heavy machines in the transportation sectors. The Pulse Width Modulated (PWM) inverters generally face the problem of Common Mode Voltages (CMV) which lead to the shaft voltage, and leakage currents which may result in electrical faults in the VSDs. These are the main root causes for the electrically provoked failure of bearing elements. This paper exhibits a new Hybrid Asymmetric Cascaded (HAC) topology with a half-height (HH) PWM technique which focuses on the mitigation of CMV without using any external hardware components. The circuit and control technique is implemented for odd levels starting from 3 levels up to 21 levels using MATLAB Simulink platform and the results are analyzed for the variation of CMV with other parameters such as levels of inverters, Total Harmonic Distortion (THD), different loading conditions, and other constraints of the load. The literature emphasized the trade-off between Total Harmonic Distortion (THD) and CMV, which is attempted to be kept well below IEEE's allowable bounds.