Low-Power Design of Advanced Image Processing Algorithms under FPGA in Real-Time Applications

Due to the real-time measurement required for image processing in practice, image processing technology is increasingly supplemented by hardware, such as using DSP (Digital Signal Processing) chips (image processing specific chips). However, when storing and processing large amounts of data, using DSP for image processing also has problems such as slow processing speed and poor real-time performance of the system. This article combines the embedded cache module in the IP core of FPGA (Field Programmable Gate Array) with the read/write ping-pong structure to store and retrieve image data, in order to save memory space on the chip. The relatively simple algorithm functions and parallel computing of FPGA, combined with a pipeline structure, shorten the image preprocessing time and solve the problem of poor real-time image processing. The experimental results show that due to the increase in workload, the static power consumption of FPGA algorithm design only increased from lW to 1.242W, while the static power consumption of traditional design increased from 1.009W to 1.578W; The dynamic power consumption of FPGA algorithm design has increased from 1.005W to 1.489W.