Simple and Linear Fast Adder of Multiple Inputs and Its Implementation in a Compute-In-Memory Architecture

A Simple and Linear Fast Adder is proposed that supports parallel addition. Its Compute-In-Memory architecture maximizes efficiency and performance of operations ranging from addition to matrix multiplication. The simple and linear topology of the adder allows for scalability past 64-bit architecture. Copies of the adder can be connected in parallel to generate a rectangular grid that performs addition of multiple inputs and scalar multiplication of two inputs. This grid can be scaled to support efficient matrix multiplication.