A sum of absolute differences implementation in FPGA hardware

In this paper we propose a new hardware unit that performs a 16/spl times/1 SAD operation. The hardware unit is intended to augment a general-purpose core. Further we show that the 16/spl times/1 SAD implementation used can be easily extended to perform the 16/spl times/16 SAD operation, which is commonly used in many multimedia standards, including MPEG-1 and MPEG-2. We have chosen to implement the 16/spl times/1 SAD operation in field-programmable gate arrays (FPGA), because it provides increased flexibility, sufficient performance, and faster design times. We performed simulations to validate the functionality of the 16/spl times/1 SAD implementation using the MAX+plus 11 (version 9.23 BASELINE) software from Altera and synthesis using the FPGA Express (version 3.4) software from Synopsis. Targeting the Altera's FLEX20KE family, synthesis of our 16/spl times/1 SAD unit produced the following results for area and clock frequency: 1699 look-up tables (LUT) and 197 MHz, respectively.