Acceptance Criteria for Good Solder Joint Reliability On Wafer Level Chip Scale Package (WLCSP) at Component Level

Wafer Level Chip Scale Packaging (WLCSP), known for its compactness, has found its way into new application domains such as mobile devices, personal phones, wireless modems, and automotive systems. These areas demand prolonged operational lifetimes and reliable performance, especially at elevated storage temperatures. WLCSP is constructed with a copper conductive layer sandwiched between two cost-effective dielectric layers. The bump structure comprises eutectic solder and the copper core of the under-bump metallization (UBM). The challenges pertaining to solder joint reliability involve potential failure mechanisms during manufacturing. These mechanisms include the time dependent phenomena of Depletion of Copper UBM (Cu) interfaces, delamination between Polyimide layer and Copper UBM, which weakens the attachment interfaces, void formation between IMC interfaces of Cu3Sn & Cu6Sn5. This paper aims to explore the relationship between Intermetallic (IMC) growth as observed through cross-section inspections; solder bump shear strength and the shear off failure modes after High Temperature Storage@175 deg C from 0 hours to 2000hrs. A similar assessment was conducted using High Temperature Storage Life at 105 deg C and 190 deg C for IMC growth between a SACQ solder bump and the Cu of the UBM as well. The novelty of this work lies in establishing acceptance criteria for reliable solder joint performance during High Temp Storage HTSL at 175 deg C (accelerate stress by 2X-Arhennius Model), based on IMC growth, solder bump shear strength and the shear off failure mode data. This focus is specifically directed towards wafer level chip scale packaging at component level. This study contributes to an enhanced understanding of mechanical performance and material properties, facilitating the structural characterization of IMC interconnects following thermal aging for WLCSP package.