A 40MHz Skewed Crystal Oscillator with Duty Cycle Corrector and Frequency Doubler for WIFI 6 in a 22nm CMOS

In this paper, a crystal oscillator structure exhibiting high jitter performance for a low-noise frequency synthesizer is presented. We propose a scheme to control the np-skewed transconductance to achieve the optimum operation point of both oscillation and phase noise in terms of power consumption. Designed as part of the 22nm CMOS process, the 40 MHz crystal oscillator achieves 93.7 fs RMS jitter in the 1 kHz to 1 MHz section and -149.4 dBc/Hz at 10kHz.