FPGA-Oriented Target Detection Accelerator Design

Target detection is widely applied in fields such as face recognition, autonomous driving, and industrial automation. However, when deploying target detection models based on convolutional neural networks on resource-constrained embedded platforms, issues like high computational complexity, long execution times, and significant on-chip memory usage arise. To address these challenges, this paper presents a target detection accelerator design based on Field Programmable Gate Array (FPGA). Firstly, the computational workload of convolutional neural networks is reduced by merging convolutional layers with batch normalization layers. Secondly, to mitigate on-chip storage space concerns, on-chip data fixed-point quantization is employed to decrease on-chip memory consumption. Subsequently, to tackle the issue of long execution times, a convolution calculation module based on the Winograd algorithm is designed, which reduces computation latency. Finally, a dual-buffer pipeline architecture is devised to optimize memory bandwidth. Experimental results demonstrate that the proposed solution accelerates YOLOv4-tiny on the ZYNQ-7020, achieving a performance of 21.35 GOP/s. The energy efficiency is 32.56 times higher than CPU and 9.76 times higher than GPU. Additionally, the convolution calculation module in this paper reduces inference time by 15% compared to the sliding window convolution calculation method.