Design of IRIG_B code Decoder for nuclear Power Plant Time Unification System

Aiming at the problems of low precision and poor working stability of the microcontroller-based IRIG-B decoder, an FPGA-based IRIG-B decoding design scheme is proposed. Considering the IRIG-B code in the transmission process due to the existence of circuit parasitic effects and random noise, the signal waveform will produce the burr problem, the design is based on the combination of Schmitt trigger and median filter hardware to completely eliminate the burr and noise on the stability of the system, over the Questa simulation experiments verified the decoding accuracy of the scheme and the advantages of stability.