Wafer-scale VLSI realization using programmable architecture

Recently, many very large scale integrations (VLSIs) or processors are integrated onto one place in data centers, artificial intelligence (AI) centers, supercomputers, and so on. In such cases, communication latency and throughput between processors invariably become main concerns. The latency, throughput, and power consumption of a network on a chip are superior to those of external communication between VLSI chips. Therefore, we propose a wafer-scale VLSI to improve the various communication shortcomings. However, wafers have many defects during the production phase. In current fabrications, even if each die size is sufficiently small, the yield ratio of the chips is limited to less than 90 %. Therefore, a wafer-scale VLSI must have many defects. However, if a programmable architecture could be introduced to wafer-scale VLSIs, then defect regions could be avoided. Non-defect regions could be used for operations. This paper therefore presents a wafer-scale VLSI realization using programmable architecture.