Electrical Noise Analysis of Polarity Gate JLTFET

This paper studies the noise characteristics of polarity gate junctionless TFET (PG JLTFET). The current simulation-based study aims to explore and evaluate the device’s frequency response to noise under different conditions. Some of the characteristics presented versus gate-to-source voltages are noise conductance, cross correlation, minimum noise figure, gate and drain autocorrelation, for device channel lengths of 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, and 40 nm. The Silvaco two-dimensional device simulator ATLAS is used to perform the numerical simulation used as a validation tool. The noise characteristics of the junctionless device were found demonstrating excellent characteristics.