Implementation of Successive Cancellation Polar Decoder Architecture

Polar codes have been adopted as error correction codes for control channels in 5G New Radio through the 3rd Generation Partnership Project (3GPP) standardization. The main requirement for 5G technology is to support maximum bandwidth and throughput along with low-complex error correction codes of larger block sizes. Polar codes achieve channel capacity closer to the Shannon limit. The challenges involved in the hardware implementation of the polar decoder have made it a widely researched topic in recent times. Different hardware architectures have been proposed for successive cancellation and successive cancellation list decoding algorithms. In this work using the semi-parallel successive cancellation decoding architecture, a polar decoder has been designed. In order to realize a system-level design, the decoder has been packaged as an AXI4-Lite IP and integrated into a Zynq-based block design using Rapid Prototyping of Hardware Accelerators on Xilinx FPGAs (RPHAX) framework. The resulting design has been deployed on a PYNQ FPGA. On the software side, the PYNQ framework has been utilized to write inputs to the slave registers and report the corresponding output. The implementation of this design as a soft logic on FPGA enables it to be leveraged by any application running on the processing system. A modification in the decoder architecture has also been attempted that shows a significant reduction in power and number of clock cycles by 50% and 33.64% respectively with an increase in the throughput by 58.3%.